| 摘要 |
Systems and methods for using carry-less multiplication (CLMUL) to implement erasure code are provided. An embodiment method of using CLMUL to implement erasure code includes initiating, with a processor, a first CLMUL call to calculate a first product of a data bit word and a constant, partitioning, with the processor, the first product into a high portion and a low portion, and initiating, with the processor, a second CLMUL call to calculate a second product of the high portion and a hexadecimal number portion, a bit size of the second product less than a bit size of the first product. The second product, or a third product generated by a third CLMUL call, is used to calculate a parity bit. Because the second product or the third product has a number of bits equivalent to the number of bits used by the processor, the erasure codes are more efficiently implemented. |
| 主权项 |
1. A method of using Carry-less Multiplication (CLMUL) to implement erasure code, comprising:
dividing, with a processor, an input data into a plurality of data bit words, each data bit word being sized to a native processor word width; initiating, with the processor, a first CLMUL call to calculate a first product of a first data bit word and a constant, the first data bit word being one of the plurality of data bit words; partitioning, with the processor, the first product into a high portion and a low portion, the low portion being sized to the native processor word width; initiating, with the processor, a second CLMUL call to calculate a second product of the high portion and a hexadecimal number portion, a bit size of the second product less than a bit size of the first product; partitioning, with the processor, the second product into a high portion and a low portion, the low portion being sized to the native processor word width; initiating, with the processor, a third CLMUL call to calculate a third product of the high portion of the second product and the hexadecimal number portion, a bit size of the third product less than a bit size of the second product; and generating, with the processor, a parity bit word of an erasure code symbol according to an exclusive or (XOR) operation on the third product, the low portion of the first product, and the low portion of the second product. |
