3D INTEGRATED CIRCUIT PACKAGE WITH THROUGH-MOLD FIRST LEVEL INTERCONNECTS

摘要

3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.

主权项

1. A method of fabricating a semiconductor die pair, the method comprising:
bonding an active side of each of a plurality of singulated first dies to an active side of a corresponding one of a plurality of second dies on a wafer to form wafer-level first and second die pairs, each of the plurality of singulated first dies smaller in area than the corresponding one of the plurality of second dies; forming a molding layer above the wafer-level first and second die pairs; grinding the molding layer to expose each of the plurality of singulated first dies and interconnect bumps of each of the plurality of second dies; and subsequent to grinding the molding layer, singulating the first and second die pairs to form a plurality of singulated first and second die pairs.