| 发明名称 | Staggered write and verify for phase change memory | ||
| 摘要 | A method for storing a data value in a memory cell is provided. The data value includes one of a first data value and a second data value respectively represented by a first and a second programmable resistance ranges. The method includes, within a write cycle, storing the first data value in the memory cell by applying a first verify operation having a first verify period and a first write operation having a first write period, or storing the second data value in the memory cell by applying a second verify operation having a second verify period longer than the first verify period and a second write operation having a second write period shorter than the first write period. The write cycle is shorter than a sum of the first write period and the second verify period. | ||
| 申请公布号 | US9159412(B1) | 申请公布日期 | 2015.10.13 |
| 申请号 | US201414331487 | 申请日期 | 2014.07.15 |
| 申请人 | Macronix International Co., Ltd. | 发明人 | Hung Chun-Hsiung;Wang Tien-Yen |
| 分类号 | G11C11/34;G11C13/00 | 主分类号 | G11C11/34 |
| 代理机构 | Haynes Beffel & Wolfeld LLP | 代理人 | Wu Yiding;Haynes Beffel & Wolfeld LLP |
| 主权项 | 1. A method for storing a data value in a memory cell, the data value including one of a first data value and a second data value respectively represented by a first and a second programmable resistance ranges, comprising: within a write cycle, storing the first data value in the memory cell by applying a first verify operation having a first verify period and a first write operation having a first write period, or storing the second data value in the memory cell by applying a second verify operation having a second verify period longer than the first verify period and a second write operation having a second write period shorter than the first write period, wherein the write cycle is shorter than a sum of the first write period and the second verify period. | ||
| 地址 | Hsinchu TW | ||