Multithreaded processor with multiple concurrent pipelines per thread

摘要

A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

主权项

1. A multithreaded processor comprising:
a hardware thread unit including a memory unit; an instruction decoder coupled to the hardware thread unit; and a plurality of execution units coupled to the instruction decoder, the execution units including an interleaved multithreaded instruction pipeline configured to process instructions issued in an instruction issuance sequence for a plurality of threads for a plurality of hardware thread units, the interleaved multithreaded instruction pipeline having execution stages concurrently executable for a first instruction and a second instruction issued by a program thread for an execution unit;
wherein the execution unit independently executes the decoded instructions of the program thread to completion in the order the first instruction and the second instruction are received;wherein on a processor clock cycle one of the plurality of threads is permitted to issue instructions, the thread permitted to issue instructions varying over a plurality of clock cycles in accordance with the instruction issuance sequence;wherein the instructions are pipelined to permit a thread to support multiple concurrent instruction pipelines; andwherein the pipelined instructions include an instruction having a pipeline with a computational cycle which is longer than an instruction issue cycle of the multithreaded processor, and wherein results for a first instruction for a program thread are always written to a register file before the results are needed by a second instruction for the program thread without stalling the second instruction and without dependency checking and bypassing hardware.