Embedded interlevel dielectric barrier layers for replacement metal gate field effect transistors

摘要

A semiconductor structure may be formed by forming a sacrificial gate above a substrate covered by a hard mask, depositing a first interlevel dielectric (ILD) layer above the sacrificial gate, recessing the first ILD layer to a thickness less than the height of the sacrificial gate, depositing an etch barrier layer above the first ILD layer, depositing a second ILD layer above the etch barrier layer, planarizing the second ILD layer and the etch barrier layer to expose the hard mask using the hard mask as a planarization stop, removing the hard mask and sacrificial gate to form a gate cavity, forming a replacement metal gate in the gate cavity, removing the second ILD layer, and planarizing the replacement metal gate using the etch barrier layer as a planarization stop. A supplementary electrode layer may be formed above the replacement metal gate prior to planarizing the replacement metal gate.

主权项

1. A method of forming a semiconductor structure, the method comprising:
forming a sacrificial gate above a substrate, wherein a top surface of the sacrificial gate is covered by a hard mask; depositing a first interlevel dielectric (ILD) layer above the sacrificial gate; recessing the first ILD layer to a thickness less than the height of the sacrificial gate; depositing an etch barrier layer over the first ILD layer; depositing a second ILD layer above the etch barrier layer; planarizing the second ILD layer and the etch barrier layer to expose the hard mask using the hard mask as a planarization stop; removing the hard mask and the sacrificial gate to form a gate cavity; forming a replacement metal gate in the gate cavity; removing the second ILD layer; planarizing the replacement metal gate using the etch barrier layer as a planarization stop; replacing a top portion of the replacement metal gate with a gate cap; depositing a third ILD layer above the gate cap and the etch barrier layer; etching the third ILD layer, the etch barrier layer, and the first ILD layer to form a contact cavity self-aligned to the gate cap exposing at least a portion of a source/drain region adjacent to the replacement metal gate; and forming a metal contact in the contact cavity.