Soft error protection device

摘要

A soft error protection device includes a soft error resilient latch (SERL) and a latch coupled to a detection device and receiving a soft error pulse and a clock (CLK) signal respectively outputted by an electronic element and a CLK generator. The SERL delays the soft error pulse. In the period of a negative level of the CLK signal, the SERL stores the delayed soft error pulse corresponding to the negative level and used as a first detection data. Meanwhile, the latch stores the soft error pulse as a second detection data. The detection device receives the CLK signal, the first and second detection datum, and compares the first and second detection datum to send out a detection signal when the CLK signal rises from the negative level to a positive level.

主权项

1. A soft error protection device comprising:
a soft error resilient latch (SERL) coupled to an electronic element and a clock (CLK) generator, receiving a soft error pulse and a clock (CLK) signal respectively outputted by said electronic element and said CLK generator, and delaying said soft error pulse, and said SERL stores delayed said soft error pulse corresponding to said negative level of said clock signal in a period of said negative level, and said delayed said soft error pulse stored by said SERL is used as a first detection data; a first latch coupled to said electronic element and said clock generator to receive said soft error pulse and said clock signal, and said first latch stores said soft error pulse corresponding to said negative level in said period of said negative level, and said soft error pulse stored by said first latch is used as a second detection data; and a detection device coupled to said SERL, said first latch and said clock generator to receive said clock signal, said first and second detection datum, and comparing said first and second detection datum to send out a detection signal when said clock signal rises from said negative level to a positive level, and said SERL further comprises:
a first electronic switch coupled to a high-voltage terminal and receiving a low-level signal to be turned on;a second electronic switch coupled to said first electronic switch and said electronic element and receiving said soft error pulse;a third electronic switch coupled to said second electronic switch, said clock generator and said detection device to receive said clock signal, and said third electronic switch is turned on in said period of said negative level;a fourth electronic switch coupled to said third electronic switch and coupled to said clock generator through a first inverter to receive reversed said clock signal, and said fourth electronic switch is turned on in said period of said negative level;a fifth electronic switch coupled to said fourth electronic switch and said electronic element to receive said soft error pulse; anda sixth electronic switch coupled to said fifth electronic switch and a low-voltage terminal and receiving a high-level signal to be turned on, and said high-level signal and said low-level signal gradually respectively descends and rises in said period of said negative level whereby said sixth electronic switch and said first electronic switch delay time that said soft error pulse is stored in output parasitic capacitances of said third and fourth electronic switches through said second and third electronic switches.