发明名称 Signal receiving apparatus and signal receiving method
摘要 A signal receiving apparatus, applicable in a wireless system calibrating direct current offset, includes: an adjusting circuit arranged to receive an receiving signal having a first DC (Direct Current) signal, and adjust the first DC signal to generate the receiving signal having a second DC signal according to an adjusting signal; a first arithmetic circuit arranged to generate an error signal according to the second DC signal and a target DC signal; and a second arithmetic circuit arranged to calculate an error signal slope according to the error signal, and update the adjusting signal according to the error signal slope and the error signal.
申请公布号 US9118523(B2) 申请公布日期 2015.08.25
申请号 US201313956545 申请日期 2013.08.01
申请人 MSTAR SEMICONDUCTOR, INC. 发明人 Su Yu-Che;Tung Tai-Lai
分类号 H04L25/06 主分类号 H04L25/06
代理机构 WPAT, PC 代理人 WPAT, PC ;King Justin
主权项 1. A signal receiving apparatus, applicable in a wireless system, comprising: an adjustment circuit, configured to receive a received signal having a first direct current (DC) signal and to adjust the first DC signal according to an adjustment signal to generate an adjusted receiving signal having a second DC signal; a first calculation circuit, configured to generate an error signal according to a comparison of the second DC signal with a target DC signal, the first calculation circuit comprising: an analog to digital converter (ADC), configured to convert the second DC signal from analog form to digital form; anda first digital processing circuit, configured to calculate the error between the second DC signal and the target DC signal to generate the error signal, the first digital processing circuit comprising: a first logic circuit, configured to generate a differential calculus signal according to the second DC signal and a prior DC signal;a second logic circuit, configured to generate an integral calculus signal and the prior DC signal by operating integral calculus on the differential calculus signal; anda third logic circuit, configured to generate the error signal according to the integral calculus signal and the target DC signal; and a second calculation circuit, configured to generate a change rate according to the error signal and to update the adjustment signal according to the change rate and the error signal.
地址 Hsinchu Hsien TW