发明名称 Semiconductor devices and method of making the same
摘要 In one embodiment, the semiconductor devices relate to using one or more super junction trenches for termination.
申请公布号 US9112026(B2) 申请公布日期 2015.08.18
申请号 US201213654143 申请日期 2012.10.17
申请人 Semiconductor Components Industries, LLC 发明人 Hossain Zia;Vavro Juraj;Moens Peter
分类号 H01L29/66;H01L29/78;H01L29/06 主分类号 H01L29/66
代理机构 Noon Intellectual Property Law, P.C. 代理人 Noon Intellectual Property Law, P.C.
主权项 1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type, wherein the first conductivity type is a n-type conductivity; a first semiconducting layer of the first conductivity type overlying the semiconductor substrate, wherein the first semiconducting layer is an epitaxial layer; and an edge termination structure surrounding an active region of the semiconductor device, wherein the edge termination structure comprises one or more first super junction trenches disposed in the first semiconducting layer, wherein the first super-junction trenches each comprise: a first semiconducting region having a second conductivity type, wherein the second conductivity type is a n-type conductivity;a second semiconducting region adjacent to the first semiconducting region, wherein the second semiconducting region has a third conductivity type, wherein the third conductivity type is a p-type conductivity, and wherein the second semiconducting region comprises a first p-well region that is adjacent to the first semiconducting layer;a first buffer region adjacent to the second semiconducting region, wherein a portion the second semiconducting region is disposed between the first semiconducting region and the first buffer region;a third semiconducting region adjacent to the first buffer region, wherein the third semiconducting region has the third conductivity type, and wherein the third semiconducting region comprises a second p-well region that is adjacent to the first semiconducting layer;a fourth semiconducting region adjacent to the third semiconducting region, wherein the fourth semiconducting region has the second conductivity type, and wherein a portion of the third semiconducting region is disposed between the first buffer region and the fourth semiconducting region; anda first conducting region electrically coupling the second semiconducting region to the third semiconducting region, wherein the first conducting region is adjacent the first p-well region of the second semiconducting region and the second p-well region of the third semiconducting region.
地址 Phoenix AZ US