STACKED SEMICONDUCTOR PACKAGE

摘要

Provided is a stacked semiconductor package which can minimize a limitation generated in designing a lower semiconductor chip according to the property of an upper semiconductor chip stacked. The stacked semiconductor package according to the present invention includes: a lower chip which has a penetration electrode region where penetration electrodes are arranged; and at least one upper chip which is stacked on the lower chip and has a pad region where pads corresponding to the penetration electrodes are arranged. The pad region is arranged along a center axis which divides the active surface of the upper chip. The center axis arranged in the pad region of the upper chip is placed in a position which is shifted from the center axis of the major-axis direction of the active surface of the lower chip.