发明名称 INTEGRATED CIRCUIT FAILURE PREDICTION USING CLOCK DUTY CYCLE RECORDING AND ANALYSIS
摘要 A system is disclosed, which may include a clock distribution circuit. The clock distribution circuit may include a duty cycle controller to distribute a clock output signal to a plurality of remote locations on a clock grid. The duty cycle controller may adjust, in response to a duty cycle control signal, a duty cycle of the clock output signal. The clock distribution circuit may also include a duty cycle measurement unit, to measure the duty cycle of the clock output signal at one of the remote locations, generate the duty cycle control signal, and generate and write duty cycle data values to a memory unit. The system may also include control logic to calculate and transmit a clock distribution circuit end-of-life date, by applying a model to stored duty cycle data values and to a duty cycle controller adjustment state.
申请公布号 US2015171835(A1) 申请公布日期 2015.06.18
申请号 US201314103958 申请日期 2013.12.12
申请人 International Business Machines Corporation 发明人 Gentner Thomas;Gungl Klaus P.;Hutzl Guenther
分类号 H03K3/017 主分类号 H03K3/017
代理机构 代理人
主权项 1. A system comprising: a clock distribution circuit having: a duty cycle controller, designed to: receive a reference clock input;output, in response to the reference clock input, a clock output signal on a clock output; andadjust, in response to a duty cycle control signal, a duty cycle of the clock output signal;a clock grid, coupled to the clock output and designed to distribute the clock output signal to a plurality of remote locations;a duty cycle measurement unit, designed to: measure the duty cycle of the clock output signal at one of the remote locations and at a plurality of time intervals;generate duty cycle data values for the clock output signal at the plurality of time intervals;generate the duty cycle control signal based on at least one of the duty cycle data values; andwrite the duty cycle data values to a memory unit designed to store a plurality of duty cycle data values; andcontrol logic designed to: calculate a predicted end-of-life (EOL) date for the clock distribution circuit by applying a model to: duty cycle data values from the memory unit; andan adjustment state of the duty cycle controller;transmit the predicted EOL date, in response to a failure prediction request.
地址 Armonk NY US