NONVOLATILE MEMORY AND ELECTRONIC DEVICE

摘要

The embodiments of the present invention disclose a nonvolatile memory and an electronic device, where each time the nonvolatile memory is powered on, an exchanger is used to implement a random exchange of at least one address subsignal and its inverted signal in a bank decoder and/or a row decoder in a bank and/or a column decoder in a bank, which causes that data stored before the nonvolatile memory is powered off is interrupted when the nonvolatile memory is powered off and then powered on and that data stored in the nonvolatile memory cannot be read sequentially from original storage addresses to achieve an encrypting effect and increase security of the data stored in the nonvolatile memory.

主权项

1. A nonvolatile memory, comprising:
a bank decoder and at least two banks, and the bank comprises a storage array, a row decoder of the storage array, and a column decoder of the storage array; and a random number generator and n1 first exchangers disposed between a first signal generator and a first decoder of the bank decoder, and one of the first exchangers corresponds to one bank address subsignal of the bank decoder, wherein: the random number generator is configured to: when the nonvolatile memory is powered on, randomly generate a selection signal for each first exchanger and send the generated selection signal to a first exchanger corresponding to the selection signal; and the i1th first exchanger of the bank decoder is configured to: receive the i2th bank address subsignal corresponding to the i1th first exchanger and an inverted signal of the i2th bank address subsignal; when a received selection signal is a first signal, output the i2th bank address subsignal as the i2th bank address subsignal to the first decoder and output the inverted signal of the i2th bank address subsignal as the inverted signal of the i2th bank address subsignal to the first decoder; when the received selection signal is a second signal, output the inverted signal of the i2th bank address subsignal as the i2th bank address subsignal to the first decoder and output the i2th bank address subsignal as the inverted signal of the i2th bank address subsignal to the first decoder; and 1≦i1≦n1, 1≦i2≦m1, and 1≦n1≦m1, where m1 is a total number of bank address subsignals.