| 摘要 |
A method for manufacturing a field effect transistor of a non-planar type, comprising the steps of:
a. providing a substrate having an initially planar front main surface;
b. providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate, in between the shallow trench isolation structures, wherein the top surfaces of the shallow trench isolation structures and the fin structures are abutting on a common planar surface, and wherein the sidewalls of the fin structures are fully concealed by the shallow trench isolation structures;
c. forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface;
d. forming dielectric spacer structures around the dummy gate structure;
e. removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures; and
f. thereafter, removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench;
g. thereafter, forming a final gate stack in the gate trench. |
