发明名称 |
Semiconductor package with ultra-thin interposer without through-semiconductor vias |
摘要 |
There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer. |
申请公布号 |
US9013041(B2) |
申请公布日期 |
2015.04.21 |
申请号 |
US201113339234 |
申请日期 |
2011.12.28 |
申请人 |
Broadcom Corporation |
发明人 |
Karikalan Sampath K. V.;Zhao Sam Ziqun;Hu Kevin Kunzhong;Khan Rezaur Rahman;Vorenkamp Pieter;Chen Xiangdong |
分类号 |
H01L23/538;H01L23/48;H01L23/498;H01L23/522;H01L25/065;H01L23/31 |
主分类号 |
H01L23/538 |
代理机构 |
McDermott Will & Emery LLP |
代理人 |
McDermott Will & Emery LLP |
主权项 |
1. A semiconductor package comprising:
an interposer substantially consisting of a dielectric material including first routing traces and second routing traces, the first routing traces and the second routing traces consisting of one or more conductive materials, the first routing traces disposed in a fan-out arrangement, the second routing traces disposed in an interconnecting arrangement; a package substrate coupled to a first surface of the interposer; a first active die coupled to a second surface of the interposer, said first active die configured to communicate electrical signals to the package substrate through the first routing traces; and a second active die coupled to the second surface of the interposer, the second active die configured to communicate chip-to-chip signals with the first active die through the second routing traces. |
地址 |
Irvine CA US |