发明名称 |
CHIP-STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME |
摘要 |
A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other. |
申请公布号 |
US2015102468(A1) |
申请公布日期 |
2015.04.16 |
申请号 |
US201414509317 |
申请日期 |
2014.10.08 |
申请人 |
KANG Un-Byoung;CHO Tae-Je;ROH Byung-Hyug |
发明人 |
KANG Un-Byoung;CHO Tae-Je;ROH Byung-Hyug |
分类号 |
H01L25/065;H01L23/48;H01L23/31 |
主分类号 |
H01L25/065 |
代理机构 |
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代理人 |
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主权项 |
1. A chip-stacked semiconductor package comprising:
a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member, and a first through-silicon via (TSV), the first TSV electrically connected to the second connection member, the second back surface being opposite to the second front surface, and the second connection member on the second front surface; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other. |
地址 |
Hwaseong-si KR |