| 摘要 |
A system on chip including a configurable image processing pipeline comprises: a first image processing module which processes a bus and image data which is connected and corresponded to the bus; a first image processing stage which transmits any one of first image data and second image data outputted from the bus to any one of the bus and the first image processing module through a first bypass path, in response to the first control signals; and a second image processing stage which transmits any one of third image data outputted from the first image processing module and fourth image data outputted from the bus to the bus through any one of a second bypass path and a second scaler path, in response to the second control signals. |
