| 摘要 |
The present invention relates to a semiconductor memory apparatus, comprising: an input data bus inversion unit which determines whether a plurality of input data are inverted or not based on an operating mode signal and a plurality of input data so as to generate a plurality of conversion data, wherein a plurality of conversion data are transmitted by a data transmission line; a data input line; a termination unit which terminates the data input line in response to the operating mode signal; a data recovery unit which receives a plurality of conversion data to generate a plurality of storage data; and a memory bank which stores a plurality of storage data. |
