Methods and system for analysis and management of parametric yield

摘要

Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

主权项

1. A method of identifying a location of anomalous functionality on a semiconductor chip, said method comprising:
by a computer:
determining at least one of spatial distribution of on-current within said semiconductor chip and spatial distribution of off-current within said semiconductor chip;converting one of said spatial distribution of on-current and said spatial distribution of said off-current into an estimated spatial temperature distribution map; andgenerating a measured temperature distribution map of said semiconductor chip in an on-state or an off-state for comparison with said estimated spatial temperature distribution map.