Stacked composite device including a group III-V transistor and a group IV lateral transistor

摘要

In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.

主权项

1. A stacked composite device having a composite drain, a composite source, and a composite gate, said stacked composite device comprising:
a group IV lateral transistor; a group III-V transistor stacked over said group IV lateral transistor; a drain electrode of said group IV lateral transistor being in direct contact with a source electrode of said group III-V transistor, said source electrode of said group III-V transistor situated on said drain electrode of said group IV lateral transistor; a source of said group IV lateral transistor being coupled to a gate of said group III-V transistor to provide said composite source on a top side of said stacked composite device; a drain of said group III-V transistor providing said composite drain on said top side of said stacked composite device; a gate of said group IV lateral transistor providing said composite gate on said top side of said stacked composite device; a substrate of said group IV lateral transistor being on a bottom side of said stacked composite device; one of a drain electrode of said group III-V transistor and said source electrode of said group III-V transistor being electrically coupled to a respective drain or source pad on an opposite side of said group III-V transistor by at least one through-substrate via.