发明名称 SYNCHRONIZATION SYSTEM AND FREQUENCY DIVISION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a synchronization system that prevents the occurrence of a timing violation due to a clock skew between a frequency division circuit and a first device.SOLUTION: The synchronization system includes: the frequency division circuit for frequency-dividing a reference clock by a first frequency division ratio set by a frequency division ratio setting signal to generate a frequency-divided clock; the first device, which operates in synchronization with the reference clock; a second device that operates in synchronization with the frequency-divided clock; a frequency division ratio detection circuit for, at every single period of the frequency-divided clock, outputting a count value counted in synchronization with the reference clock and, on the basis of the count value, detecting a frequency division ratio of the frequency-divided clock to be output as a second frequency division ratio; and a decoder for generating strobe signals to control timings when the first device inputs/outputs signals from/to the second device, on the basis of the count value and the second frequency division ratio. The first device communicates with the second device via a bus that operates in synchronization with the frequency-divided clock, on the basis of the strobe signals.
申请公布号 JP2015053638(A) 申请公布日期 2015.03.19
申请号 JP20130186344 申请日期 2013.09.09
申请人 MEGA CHIPS CORP 发明人 YAMASHITA KAZUNORI
分类号 H03K23/64;G06F1/08;H03L7/08 主分类号 H03K23/64
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