| 摘要 |
<p>An instruction scheduling method and device for scheduling instructions, relating to the field of communications, that enable a processor or an assembly line to function normally and enhance the accuracy of scheduling. The method comprises: establishing a data dependency graph; extracting from the data dependency graph k instructions to conduct scheduling to obtain m very long instruction words (VLIW) for each cycle such that the VLIW in a same cycle can be executed parallelly and that for any two adjacent cycles, there is no dependency between the instruction at the t-th instruction slot of any VLIW in the latter cycle and the instruction at the (t+1)-th instruction slot of any VLIW in the former cycle, where 0≤k≤m*n, n is the number of instruction slots in a VLIW, n is an integer greater than or equal to 1, m is the number of VLIW in each cycle, m is an integer greater than or equal to 1, and t is an integer greater than or equal to 1 and smaller than or equal to n-1.</p> |
