发明名称 |
Shallow trench isolation for a memory |
摘要 |
In some embodiments, a gate structure with a spacer on its side may be used as a mask o form self-aligned trenches in microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure. |
申请公布号 |
US8963220(B2) |
申请公布日期 |
2015.02.24 |
申请号 |
US201314043704 |
申请日期 |
2013.10.01 |
申请人 |
Micron Technology, Inc. |
发明人 |
Grossi Alessandro;Mariani Marcello;Cappelletti Paolo |
分类号 |
H01L29/76;H01L29/788;H01L27/115;H01L29/423 |
主分类号 |
H01L29/76 |
代理机构 |
Dorsey & Whitney LLP |
代理人 |
Dorsey & Whitney LLP |
主权项 |
1. An apparatus comprising:
a substrate including two parallel trenches in the substrate defining an active area between the trenches; and a floating gate structure in the active area, the active area including an unetched portion of the substrate between a trench and an edge of the floating gate structure, wherein the unetched portion of the substrate is electrically inactive, and wherein the floating gate structure includes a first dielectric layer disposed between the active area and a lower gate layer, and further includes an upper gate layer disposed on the lower gate layer. |
地址 |
Boise ID US |