发明名称 |
CONTROL CIRCUIT OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE |
摘要 |
A control circuit includes a ROM suitable for generating ROM data based on a ROM address corresponding to a predetermined operation, a command analyzing unit suitable for outputting the ROM address corresponding to the predetermined operation, generating an address storing signal in response to an operation suspension command for suspending the predetermined operation, and generating an address output signal in response to an operation resumption command for resuming the predetermined operation, an address storing unit suitable for storing a ROM address, which corresponds to the ROM address at a time point where the predetermined operation is suspended, in response to the address storing signal, and an address output unit suitable for outputting the ROM address corresponding to said time point in response to the address output signal, wherein the ROM generates ROM data for resuming the predetermined operation based on the ROM address corresponding to said time point. |
申请公布号 |
US2015019791(A1) |
申请公布日期 |
2015.01.15 |
申请号 |
US201314092430 |
申请日期 |
2013.11.27 |
申请人 |
SK hynix Inc. |
发明人 |
YOO Byoung Sung |
分类号 |
G06F12/02 |
主分类号 |
G06F12/02 |
代理机构 |
|
代理人 |
|
主权项 |
1. A control circuit of a semiconductor device, comprising:
a ROM suitable for generating ROM data based on a ROM address corresponding to a predetermined operation; a command analyzing unit suitable for outputting the ROM address corresponding to the predetermined operation, for generating an address storing signal in response to an operation suspension command for suspending the predetermined operation, and for generating an address output signal in response to an operation resumption command for resuming the predetermined operation; an address storing unit suitable for storing a ROM address, which corresponds to the ROM address at a time point where the predetermined operation is suspended, in response to the address storing signal; and an address output unit suitable for outputting the ROM address corresponding to the time point in response to the address output signal, wherein the ROM generates ROM data for resuming the predetermined operation based on the ROM address corresponding to the time point. |
地址 |
Gyeonggi-do KR |