| 发明名称 | Tracking bit cell | ||
| 摘要 | A memory macro includes a tracking circuit and a plurality of memory cells. The tracking circuit has tracking transistors configured to receive a tracking voltage value. Each memory cell of the plurality of memory cells has memory transistors configured to receive a cell voltage value different from the tracking voltage value. The tracking circuit is configured to generate a tracking signal based on which a reading signal of a memory cell of the plurality of memory cells is generated. | ||
| 申请公布号 | US8934308(B2) | 申请公布日期 | 2015.01.13 |
| 申请号 | US201113273705 | 申请日期 | 2011.10.14 |
| 申请人 | Taiwan Semiconductor Manufacturing Company, Ltd. | 发明人 | Wang Bing |
| 分类号 | G11C7/00;G11C7/02;G11C11/419 | 主分类号 | G11C7/00 |
| 代理机构 | Lowe Hauptman & Ham, LLP | 代理人 | Lowe Hauptman & Ham, LLP |
| 主权项 | 1. A memory macro comprising: a tracking circuit having tracking transistors and a power node coupled with the tracking transistors, the power node of the tracking circuit being configured to receive a first operational voltage, the first operational voltage having a first voltage level; and a plurality of memory cells, each memory cell of the plurality of memory cells having memory transistors and a power node coupled with the memory transistors, the power node of the corresponding memory cell being configured to receive a second operational voltage, the second operational voltage having a second voltage level different from the first voltage level, wherein the tracking circuit is configured to generate a tracking signal, a memory cell of the plurality of memory cells is configured to perform a read operation responsive to a reading signal, and the reading signal is generated based on the tracking signal. | ||
| 地址 | TW | ||