SYSTEM AND METHOD FOR VARIABLE FREQUENCY CLOCK GENERATION

摘要

A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.

主权项

1. A clock generation circuit, comprising:
a detection circuit configured to detect a change in a voltage supply signal coupled to the clock generation circuit; and a control circuit coupled to the detection circuit and configured to alter a control signal for regulating a current-controlled oscillator in response to detecting the change.