| 摘要 |
A scan driving circuit comprises a shift register unit and a logic circuit unit. The start pulse of an output signal (ST_(p+1)) from a (p+1)^th shift register starts between the beginning and the end of the start pulse of an output signal (ST_p) from a p^th shift register. First to Q^th enable signals sequentially occur one by one between the beginning of the start pulse of the output signal (ST_p) and the beginning of the start pulse of the output signal (ST_(p+1)). The operation of a (p′, q)^th NAND circuit is limited based on a period specifying signal. The NAND circuit generates a scan signal based only on: a signal of the output signal (ST_p) region corresponding to a first start pulse; an inverted output signal (ST_(p+1)); and a q^th enable signal (EN_q). |
