SYSTEM AND METHOD FOR SEARCHING FOR ZADOFF-CHU SEQUENCES DURING A PHYSICAL RANDOM ACCESS CHANNEL SEARCH

摘要

A system that includes an interface, a processor; and a hardware accelerator. The hardware accelerator is arranged to perform, for each Zadoff-Chu sequence of at least a first sub-set of the set of Zadoff-Chu sequences, a first hardware accelerator set of operations that includes frequency to time domain conversion to provide third intermediate vector that is associated with the Zadoff-Chu sequence. The processor is arranged to complete the Zadoff-Chu sequence search in response to the third intermediate vector—whereas the hardware accelerator and the processor are arranged to partially search the same Zadoff-Chu sequence at different periods of time.

主权项

1. A system for searching for a set of Zadoff-Chu sequences, the system comprises:
an interface that is arranged to receive a set of first antenna signals that represent input signals received by the first antenna; a processor; and a hardware accelerator; wherein the hardware accelerator is arranged to perform, for each Zadoff-Chu sequence of at least a first sub-set of the set of Zadoff-Chu sequences, a first hardware accelerator set of operations that comprises performing a frequency domain to time domain transformation of a second intermediate vector that is representative of multiplication of Zadoff-Chu sequence and a set of first received signals to provide a third intermediate vector that is associated with the Zadoff-Chu sequence; wherein the processor is arranged to perform, for each Zadoff-Chu sequence of at least a second sub-set of Zadoff-Chu sequences a first processor set of operations that comprises:
performing a search, based on the third intermediate vector, to determine whether the set of first antenna signals included a representation of the Zadoff-Chu sequence; wherein the processor is arranged to execute the first processor set of operations related to a certain Zadoff-Chu sequence when the hardware accelerator is arranged to execute the first hardware accelerator set of operations relating to another Zadoff-Chu sequence.