发明名称 Shallow trench isolation area having buried capacitor
摘要 A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.
申请公布号 US8896087(B2) 申请公布日期 2014.11.25
申请号 US201012792507 申请日期 2010.06.02
申请人 Infineon Technologies AG 发明人 Terletzki Hartmud
分类号 H01L29/00;H01L27/02;H01L49/02;H01L27/06;H01L29/94;H01L29/66 主分类号 H01L29/00
代理机构 Slater & Matsil, L.L.P. 代理人 Slater & Matsil, L.L.P.
主权项 1. A semiconductor chip comprising: a substrate comprising a surface; an active transistor region having a body region and a substrate contact region disposed at the substrate, wherein the substrate contact region is coupled to the body region of the active transistor region, and wherein the substrate contact region forms a substrate contact to the body region of the active transistor region; a shallow trench isolation (STI) area disposed at the surface and disposed at least partially between the active transistor region and the substrate contact region; at least one capacitor at least partially buried in the isolation material of the STI area; and a STI disposed at the surface, wherein the substrate contact region coupled to the body region is disposed between the STI and the STI area comprising the at least one capacitor.
地址 Neubiberg DE