Compact three dimensional vertical NAND and method of making thereof

摘要

A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.

主权项

1. A NAND device, comprising:
an array of vertical NAND strings, wherein:
each NAND string comprises a semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, and a blocking dielectric located adjacent to the charge storage region;at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate; andthe array comprises at least a 3×3 array of NAND strings; a plurality of control gate electrodes having a mesh shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, wherein:
the first control gate electrode and the second control gate electrode are continuous in the array.