MEMORY CONTROLLER AND ASSOCIATED SIGNAL GENERATING METHOD

摘要

The invention is directed to a memory controller and an associated signal generating method. By appropriately arranging a sequence according to which command signals are generated and expanding a latching interval of a part of address signals, not only the memory controller is enabled to control the DDR memory modules in a functional manner to further overcome issues of conventionally small latching intervals, but also system stability and access performance are reinforced as the memory access clock speed continue to increase.

主权项

1. A signal generating method of a memory controller, for controlling a first memory module, comprising:
generating a first clock signal, a bank control signal and a first-part address signal that have a signal period of a unit time; generating a command signal having a signal period of the unit time, wherein the command signal comprises a plurality of command groups each having a first command, a second command, a third command and a fourth command that are consecutive; and generating a second-part address signal having a signal period twice of the unit time; wherein, a first signal edge of the first clock signal occurs during latching intervals of the command signal, the bank control signal and the first-part address signal; a second signal edge of the first clock signal occurs during latching intervals of the command signal, the bank control signal, the first-part address signal and the second-part address signal; a third signal edge of the first clock signal occurs during latching intervals of the command signal, the bank control signal and the first-part address signal; and a fourth signal edge of the first clock signal occurs during the latching intervals of the command signal, the bank control signal, the first-part address signal and the second-part address signal.