Dejitter (desynchronize) technique to smooth gapped clock with jitter/wander attenuation using all digital logic

摘要

Digital logic receives a gapped and jittery clock signal with specified frequency and frequency offset allowed by specification and a reference clock signal with same specified frequency and different frequency offset allowed by specification having low jitter. The digital logic adds and/or removes cycles from the reference clock signal over an extended period of time to produce a produced clock signal with low jitter that has a frequency that approaches the frequency of the gapped and jittery clock signal. The produced clock signal being provided as feedback to the digital frequency comparator and also acts as final dejitter smooth clock output with 50% duty cycle.

主权项

1. A logic system, comprising:
a smoother circuit, configured to receive a core clock having a substantially constant period and a gapped clock, and to generate a degapped clock, wherein the gapped clock has a plurality of repeated pulse times, during which the gapped clock has a plurality of pulses substantially having a period near but not equal to the period of the core clock, wherein the gapped clock additionally has a plurality of repeated stable times, during which the gapped clock has no pulses, and wherein the repeated pulse times and the repeated stable times alternate, the smoother circuit comprising:
digital circuitry configured to generate an add/remove signal based at least in part on the gapped clock and on the degapped clock, anda pulse generator circuit configured to generate the degapped clock based on the gapped clock, the core clock, and the add/remove signal,wherein the degapped clock has a plurality of repeated pulse times, during which the degapped clock has a plurality of pulses occurring at a frequency near but not equal to the average frequency of the gapped clock, and wherein the degapped clock has a plurality of adjustment times, during which the degapped clock either has no pulses or has two pulses,wherein the pulse generator circuit is configured to generate either no pulses or two pulses during each of the adjustment times based on the add/remove signal of the digital circuitry; and a dejitter circuit, configured to receive the degapped clock and to generate an output clock, the dejitter circuit comprising:
digital circuitry configured to generate an extend/shorten signal based at least in part on the degapped clock and on the output clock, anda clock generator circuit configured to generate the output clock based at least in part on the core clock and on the extend/shorten signal,wherein the output clock has frequency substantially equal to the average frequency of the gapped clock, and has a jitter of less than about the period of the core clock.