Method for improving device performance using dual stress liner boundary

摘要

An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.

主权项

1. A method of forming an integrated circuit, comprising the steps:
forming a pmos transistor with a p-active area in an nwell; forming a nmos transistor with an n-active area adjacent to said pmos transistor where a boundary of said nwell is approximately midway between said p-active area and said n-active area; depositing a compressive contact etch stop liner over said pmos transistor and removing it from said nmos transistor; depositing a tensile contact etch stop liner over said nmos transistor and removing it from said pmos transistor; forming a parallel DSL border which lies primarily outside said nwell; and forming a perpendicular DSL border which lies primarily inside said nwell.