发明名称 DATA CONVERSION WITH REDUNDANT SPLIT-CAPACITOR ARRANGEMENT
摘要 Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant split-capacitor arrangement using a successive approximation technique can provide a fast and power efficient ADC. For example, a successive approximation capacitor arrangement may include multiple arrays with non-binary bit weights.
申请公布号 US2014247177(A1) 申请公布日期 2014.09.04
申请号 US201313783054 申请日期 2013.03.01
申请人 INFINEON TECHNOLOGIES AG 发明人 DRAXELMAYR Dieter
分类号 H03M1/12 主分类号 H03M1/12
代理机构 代理人
主权项 1. An apparatus, comprising: a first array of capacitances coupled to a common node, each successive capacitance of the first array having a capacitance value that is less than a capacitance value of a previous adjacent capacitance, according to a predetermined non-binary numerical pattern; and a second array of capacitances coupled to the common node, each capacitance of the first array having an associated capacitance within the second array with an approximately equivalent capacitance value, the first array and the second array in combination arranged to determine a digital approximation for an analog input value.
地址 Neubiberg DE