COMPRESSION STATUS BIT CACHE AND BACKING STORE

摘要

One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.

主权项

1. A memory system for determining and updating compression status for a virtually addressed unit of data, the memory system comprising:
a memory management unit configured to access a page table entry (PTE) that includes a compression cache tag line; and a cache unit configured to access a compression cache in response to the PTE being accessed and based on the compression cache tag line, wherein the compression cache tag line uniquely identifies a compression cache entry within the compression cache, and wherein the compression cache entry includes compression status bits corresponding to the PTE.