发明名称 Semiconductor device
摘要 A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. Another problem is that an increase in memory capacity leads to an increase in the area, despite an attempt at integration through advancement of transistor miniaturization. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. In addition, a plurality of memory elements each including the transistor having a trench structure and including an oxide semiconductor is stacked in a semiconductor device, whereby the circuit area of the semiconductor device can be reduced.
申请公布号 US8809870(B2) 申请公布日期 2014.08.19
申请号 US201213354617 申请日期 2012.01.20
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Yamazaki Shunpei;Godo Hiromichi
分类号 H01L29/15;H01L31/0312;H01L29/78;G11C11/403 主分类号 H01L29/15
代理机构 Robinson Intellectual Property Law Office, P.C. 代理人 Robinson Eric J.;Robinson Intellectual Property Law Office, P.C.
主权项 1. A semiconductor device comprising: a circuit comprising a first transistor; and a memory element comprising a second transistor and a capacitor, wherein the second transistor comprises: a first insulating layer;a first trench in the first insulating layer;a second trench in the first insulating layer;an oxide semiconductor layer in contact with an inner wall surface of the first trench;a second insulating layer adjacent to the oxide semiconductor layer, wherein the second insulating layer is adjacent to an inner wall surface of the second trench;a gate electrode in the first trench and adjacent to the oxide semiconductor layer with the second insulating layer interposed therebetween;a third insulating layer filling the second trench; anda source electrode or a drain electrode in contact with the oxide semiconductor layer, and wherein the memory element is stacked over the circuit.
地址 Atsugi-shi, Kanagawa-ken JP