| 发明名称 | Semiconductor memory device | ||
| 摘要 | A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock. | ||
| 申请公布号 | US8780646(B2) | 申请公布日期 | 2014.07.15 |
| 申请号 | US201213404734 | 申请日期 | 2012.02.24 |
| 申请人 | Hynix Semiconductor Inc. | 发明人 | Kim Yong-Mi |
| 分类号 | G11C7/10;G11C7/00;G11C8/00;G11C8/18 | 主分类号 | G11C7/10 |
| 代理机构 | IP & T Group LLP | 代理人 | IP & T Group LLP |
| 主权项 | 1. A semiconductor memory device comprising: a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal; and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock, wherein the enable signal comprises an On Die Termination enabling signal, and the pipe latch circuit is configured to set the output terminal of the pipe latch circuit at the predetermined voltage level when the enable signal is enabled. | ||
| 地址 | Gyeonggi-do KR | ||