Single photon counting readout chip with negligible dead time

摘要

A single photon counting pixel detector chip has a negligible dead time and consequentially high frame rates. The detector chip contains: a) a layer of photosensitive material; b) an N×M array of photo-detector diodes arranged in the layer of photosensitive material; and c) a N×M array of readout unit cells. The readout unit cell contains an input interface connected to a diode output interface, a high-gain charge to voltage amplifying device and a pixel counter being connected to an output of the high-gain voltage amplifying device. The pixel counter is split into a first number of nibble counters. The basic counter cell contains a counting element, a switch, a temporary storage element and an output stage. Additionally, the detector chip has a side shift register to read out the nibble counters row-wise with a predetermined number of nibble row selections.

主权项

1. A single photon counting pixel detector chip, comprising:
a layer of photosensitive material; an N×M array of photo-detector diodes disposed in said layer of photosensitive material, each of said photo-detector diodes having a diode output interface; a N×M array of readout unit cells, one of said readout unit cells being provided for each of said photo-detector diodes, each of said readout unit cells containing:
an input interface connected to one of said diode output interfaces;a high-gain charge to voltage amplifying means having an output;a pixel counter connected to said output of said high-gain voltage amplifying means, said pixel counter being split into a first number of nibble counters, each of said nibble counters having an individual number of bits, wherein for each of said bits, said nibble counters have a basic counter cell, said basic counter cell containing a counting element, a switch, a temporary storage element and an output stage, wherein said basic counter cells are cascaded, said temporary storage elements being implemented as an array of capacitors wherein said array of capacitors is physically placed on top of said pixel counter; and a side shift register to read out said nibble counters row-wise with a predetermined number of nibble row selections wherein data stored in said temporary storage elements on a selected nibble counter row are sent on a parallel bus as currents and are transformed into digital levels by parallel bus receivers.