发明名称 ARRAY SUBSTRATE FOR TFT-LED, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE
摘要 An array substrate, a method of manufacturing the same, and a display device are provided to effectively eliminate the afterimage phenomenon and improve the display quality of display device. A pixel electrode, a common electrode, a first TFT and a second TFT are provided in a sub-pixel region defined by Nth and (N+1)th gate lines of a plurality of gate lines and two data lines of the plurality of data lines, and a multi-dimensional electric field is formed when the pixel electrode and the common electrode are powered. A first gate electrode of the first TFT is connected to the (N+1)th gate line, a first source electrode of a first TFT is connected to one of the two data lines, a first drain electrode of the first TFT is connected to the pixel electrode; a second gate electrode of a second TFT is connected to the Nth gate line, a second drain electrode of the second TFT is connected to the pixel electrode, a second source electrode of the second TFT is connected to the common electrode; and the Nth gate line comprises any one of the plurality of gate lines except the last one, and during a gate line scanning process for one frame in the array substrate, the Nth gate line is always scanned in advance of the (N+1)th gate line.
申请公布号 US2014160416(A1) 申请公布日期 2014.06.12
申请号 US201314096798 申请日期 2013.12.04
申请人 BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. ;Boe Technology Group Co., Ltd. 发明人 Wang Xiao;Cao Kun
分类号 G02F1/1343 主分类号 G02F1/1343
代理机构 代理人
主权项 1. An array substrate for using in a TFT-LCD comprising: a transparent substrate; a plurality of gate lines and a plurality of data lines positioned crosswise on the transparent substrate to define a plurality of sub-pixel regions; and a pixel electrode, a common electrode, a first TFT and a second TFT provided in a sub-pixel region defined by the Nth and (N+1)th gate lines of the plurality of gate lines and two data lines of the plurality of data lines, and the pixel electrode and the common electrode forming a multi-dimensional electric field when powered; wherein a first gate electrode of the first TFT is connected to the (N+1)th gate line, a first source electrode of the first TFT is connected to one of the two data lines, a first drain electrode of the first TFT is connected to the pixel electrode; a second gate electrode of the second TFT is connected to the Nth gate line, a second drain electrode of the second TFT is connected to the pixel electrode, a second source electrode of the second TFT is connected to the common electrode; and the Nth gate line comprises any one of the plurality of gate lines except the last one, and during a gate line scanning process for one frame in the array substrate, the Nth gate line is always scanned in advance of the (N+1)th gate line.
地址 Beijing CN