| 摘要 |
A replica has delay time made by modeling the delay time in a semiconductor memory device and includes a first signal level conversion delay unit which receives an input signal of a CMOS voltage level, converts the input signal into a signal of a CML voltage level, and outputs the converted signal; a second signal level conversion delay unit which receives the output signal of the first signal level conversion delay unit, converts the output signal into the signal of the CMOS voltage level, and outputs the converted signal; and a CMOS level delay unit which delays the output signal of the second signal level conversion delay unit and outputs the delayed signal as an output signal. [Reference numerals] (110) First signal level conversion delay unit; (120) Second signal level conversion delay unit; (130) CMOS level delay unit |
