发明名称 System and method of electromigration mitigation in stacked IC designs
摘要 A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.
申请公布号 US8631372(B2) 申请公布日期 2014.01.14
申请号 US201213477153 申请日期 2012.05.22
申请人 YU CHI-YEH;FU CHUNG-MIN;YEH PING-HENG;TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 YU CHI-YEH;FU CHUNG-MIN;YEH PING-HENG
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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