发明名称 MEMORY WITH EXTENDED CHARGE TRAPPING LAYER
摘要 <p>A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.</p>
申请公布号 KR20140001992(A) 申请公布日期 2014.01.07
申请号 KR20137020128 申请日期 2011.12.29
申请人 SPANSION LLC 发明人 FANG SHENQING;CHEN TUNG SHENG;CHEN CHUN
分类号 H01L27/115;H01L21/8247 主分类号 H01L27/115
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