发明名称 |
Concurrent operation of plural flash memories |
摘要 |
A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed. |
申请公布号 |
US8565023(B2) |
申请公布日期 |
2013.10.22 |
申请号 |
US201213670607 |
申请日期 |
2012.11.07 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
YANG TIEN-CHUN;LEE CHIA-FU;CHIH YUE-DER |
分类号 |
G11C16/04 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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