发明名称 FREQUENCY MODULATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To restrain a circuit scale from growing in a frequency modulation circuit designable by a synchronous circuit, as well as restrain jitters in the generated frequency modulation signal.SOLUTION: When either one of a first and a second value to be accumulated is not an integer, a value-to-be-accumulated decoder 301 sequentially outputs, for example, two integers on either side of the first or the second value to be accumulated which is not an integer to an accumulator 202 each time a reference clock arrives during a period in which the first or the second value to be accumulated which is not an integer is accumulated.
申请公布号 JP2013207505(A) 申请公布日期 2013.10.07
申请号 JP20120073651 申请日期 2012.03.28
申请人 YOKOGAWA ELECTRIC CORP 发明人 SUZUKI AKIHIRO
分类号 H04L27/12;H03C3/00 主分类号 H04L27/12
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