| 摘要 |
A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer including adjusting and setting a distance between a single shadow mask installed to a mask set to be rotated and revolved and having a plurality of slits, positioning a dielectric layer deposition source to be perpendicular to the single shadow mask and a conductor layer deposition source to be oblique to the single shadow mask, and forming the dielectric layer and the conductor layer in the vacuum deposition while controlling the mask set to move along the X-, Y-, and Z-axes (the X-axis is the width direction, the Y-axis is the longitudinal direction, and the Z-axis is the height direction).
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