| 摘要 |
This processor is provided with: a first instruction processing unit (102) which, in a first mode, receives a first input including an instruction which is included in a first instruction set in order to execute scheduling and decoding of the instruction; a second instruction processing unit (103) which has a simpler configuration than the first instruction processing unit (102) and which, in a second mode, receives the first input in order to execute scheduling and decoding of the instruction; a third instruction processing unit (104) which has a simpler configuration than the first instruction processing unit (102) and the second instruction processing unit (103) and which, in a third mode, receives a second input including an instruction which is included in a second instruction set configured from a portion of the instructions in the first instruction set in order to execute scheduling and decoding of the instruction; an execution result selection unit (105) which, in accordance with the mode, selects the execution result of any one of the instruction processing units; and an instruction execution unit (106) which, in accordance with the selected execution result, executes the instruction. |
