FAST FOURIER TRANSFORM PROCESSOR USING AREA EFFICIENT MRMDC ARCHITECTURE REDUCING COMPLEX MULTIPLIERS BETWEEN DIFFERENT TWO RADIX ALGORITHM

摘要

PURPOSE: A fast Fourier transform (FFT) device which applies a low area mixed-radix multi-path delay commutator (MRMDC) structure of reducing the complex multiplier between two radix algorithms is provided to calculate a multiplication calculation, which is performed in a second stage, before an exchanger and input a calculation result to the second stage, thereby reducing the number of complex multipliers. CONSTITUTION: A switch (111) dividedly outputs the data strings of a first stage to 4 data paths. A radix-4 butterfly unit (113) performs a butterfly calculation according to a radix-4 algorithm based on 4 data strings. A multiplexer (115) receives the 4 data strings and outputs 3 data strings to 3 data paths. A complex multiplier (116) is equipped on 2 data paths among the 3 data paths. The complex multiplier multiplies and outputs the data strings and different twiddle factors. An exchanger dividedly outputs 12 data strings including the data strings to different 12 data paths.