In general, in one aspect, a display controller has non-essential portions powered off for a portion of vertical blanking interval (VBI) periods to conserve power. The portion takes into account overhead for housekeeping functions and memory latency for receiving a fist packet of pixels for a frame to be decoded during a next active period. Gating circuitry may gate power to the non-essential portions starting at beginning of the VBI periods. A latency predictor may predict the portion of the VBI periods by predicting the memory latency for a next VBI period and subtracting the predicted memory latency from the VBI period. The memory latency for the next VBI period may be predicted by adding an average difference between successive actual memory latencies for a plurality of VBI periods to an actual memory latency for previous VBI period. A constant delay may also be subtracted from the VBI period.
申请公布号
WO2013090584(A1)
申请公布日期
2013.06.20
申请号
WO2012US69521
申请日期
2012.12.13
申请人
INTEL CORPORATION;WEE, KEVIN GUAN MING;LU, CHIN SENG;LIM, PEI JIN;LIM, LEE TECK HENRY
发明人
WEE, KEVIN GUAN MING;LU, CHIN SENG;LIM, PEI JIN;LIM, LEE TECK HENRY