| 摘要 |
An OLED display comprises a plurality of pixel driver circuits (Fig. 5a; 402) on chiplets (Fig. 5a; 400), each pixel driver circuit comprising an output transistor 258 for driving an associated OLED pixel. A cascode transistor 302 on the chiplet is coupled between the output transistor drain and the anode of the associated OLED 252. A power supply is provided to the chiplet, defining a chiplet voltage range. A second connection of the associated OLED pixel is connected to an OLED voltage VCAT outside the chiplet voltage range. The OLED pixel is then driven using the pixel driver circuit over an OLED voltage range greater than the chiplet voltage range. The drain connection of the cascode transistor may be set at a voltage below a ground or negative (Vss) power supply to a chiplet. The effect of the cascode transistor 302 is to reduce voltage variations on the drain connection of driver transistor 258. The effect of parasitic diode between the output cascade and transistor drain is removed. |
