发明名称 |
Filter circuit, transmission filter circuit, semiconductor integrated circuit, communication apparatus, and timing adjustment method for filter circuit |
摘要 |
A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.
|
申请公布号 |
US8395442(B2) |
申请公布日期 |
2013.03.12 |
申请号 |
US201113240179 |
申请日期 |
2011.09.22 |
申请人 |
TOKUMARU MICHIKO;IKOMA HEIJI;OKAMOTO KOUJI;PANASONIC CORPORATION |
发明人 |
TOKUMARU MICHIKO;IKOMA HEIJI;OKAMOTO KOUJI |
分类号 |
H03K5/00 |
主分类号 |
H03K5/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|