NAND PROGRAMMING APPARATUS

摘要

PURPOSE: A NAND programming device is provided to program a NAND connected to all CPUs with a JTAG(Joint Test Action Group) port by directly controlling a BSC. CONSTITUTION: A NAND control unit(230) generates a write enable signal, a command latch enable signal, an address latch enable signal, and a chip selection signal according to a write operation command and outputs a data input and output signal corresponding to data from a CPU. A NAND bridge(240) generates a first boundary scan cell state string for the time of a write operation preparation state, a second boundary scan cell state string for the time of a write operation state, and a third boundary scan cell state string for the time of a write operation finish state. A serializer(250) writes data included in serial JTAG data in the NAND flash memory if the JTAG data reaches a boundary scan cell(122) for determining a read or write operation by successively shifting a plurality of boundary scan cells(120). [Reference numerals] (110) NAND flash; (230) NAND control unit; (240) NAND bridge; (250) Serializer; (270) IEEE 1149.1 state machine; (280) JTAG port