| 摘要 |
<P>PROBLEM TO BE SOLVED: To sufficiently ensure the processing accuracy of a layout pattern in consideration of the manufacturing process. <P>SOLUTION: A semiconductor integrated circuit layout design method of the present invention includes the steps of: selecting a plurality of partial areas that have a predetermined spacing from a reference position within a predetermined area, which is already laid out, of a semiconductor integrated circuit and have the same shape; calculating, for each of the selected partial areas, a pattern density that is the proportion of a pattern, which is laid out within each of the partial areas, in the partial area; and performing layout verification on the basis of the correlation of the pattern density between the plurality of partial areas. <P>COPYRIGHT: (C)2013,JPO&INPIT |
